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.\" ========================================================================
.\"
.IX Title "EditFiles 3pm"
.TH EditFiles 3pm "2022-10-20" "perl v5.36.0" "User Contributed Perl Documentation"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
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.SH "NAME"
Verilog::EditFiles \- Split Verilog modules into separate files.
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
See splitmodule command.
.PP
.Vb 10
\& use Verilog::EditFiles;
\& my $split = Verilog::EditFiles\->new
\& (outdir => "processed_rtl",
\& translate_synthesis => 0,
\& lint_header => undef,
\& celldefine => 1,
\& );
\& $split\->read_and_split(glob("inbound_rtl/*.v"));
\& $split\->write_files();
\& $split\->edit_file(filename=>"foo", cb => sub { return $_[0]; });
.Ve
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
Verilog::EditFiles provides a easy way to split library Verilog files that
contain multiple modules into many files with one module per file.
.SH "FUNCTIONS"
.IX Header "FUNCTIONS"
.IP "new (...)" 4
.IX Item "new (...)"
Create a new Verilog::EditFiles object. Named parameters may be specified:
.RS 4
.IP "celldefine" 4
.IX Item "celldefine"
If true, add \*(L"`celldefine\*(R" before every module statement.
.IP "lint_command" 4
.IX Item "lint_command"
For the write_lint method, the name of the linter to use. Defaults to
\&\*(L"vlint \-\-brief\*(R".
.IP "lint_header" 4
.IX Item "lint_header"
If defined, add the provided text before every module statement. Generally
used to insert lint off pragmas.
.IP "outdir" 4
.IX Item "outdir"
Name of the directory to write the output modules to. Defaults to \*(L".\*(R".
.IP "program" 4
.IX Item "program"
Name of the program to add to comments. Defaults to
\&\*(L"Verilog::EditFiles\*(R".
.IP "timescale_header" 4
.IX Item "timescale_header"
If defined, add the provided text before every module statement. Generally
set to the next needed to #include a timescale file. Use with
timescale_removal.
.IP "timescale_removal" 4
.IX Item "timescale_removal"
If set, remove any `timescales.
.IP "translate_synthesis" 4
.IX Item "translate_synthesis"
If 1, replace any synopsys translate on/offs with \*(L"`ifdef \s-1SYNTHESIS\*(R"\s0 and
\&\*(L"`endif\*(R"s. If set to a string, use that string instead of \*(L"\s-1SYNTHESIS\*(R".\s0
.IP "v_suffix" 4
.IX Item "v_suffix"
The suffix to add to convert a module name into a filename. Defaults to
\&\*(L".v\*(R".
.IP "verbose" 4
.IX Item "verbose"
If true, print what files are being read and written.
.RE
.RS 4
.RE
.ie n .IP "$self\->read_and_split([filenames])" 4
.el .IP "\f(CW$self\fR\->read_and_split([filenames])" 4
.IX Item "$self->read_and_split([filenames])"
Read from the specified filenames.
.Sp
If there is no module statement in the file, assume it is a include file,
and when write_files is called, place all of the file contents into the
output. If there is a module statement, when write_files is called place
all following output into a file named based on the module, with .v added.
.ie n .IP "$self\->\fBwrite_files()\fR" 4
.el .IP "\f(CW$self\fR\->\fBwrite_files()\fR" 4
.IX Item "$self->write_files()"
Write all of the files created by read_and_split to the outdir.
.ie n .IP "$self\->write_lint([filename=>...])" 4
.el .IP "\f(CW$self\fR\->write_lint([filename=>...])" 4
.IX Item "$self->write_lint([filename=>...])"
Create a shell script that will lint every file created by write_files. If
a \*(L"filename\*(R" parameter is not provided, \*(L"0LINT.sh\*(R" will be written in the
default outdir.
.ie n .IP "$self\->edit_file(filename=>..., cb=>sub{...})" 4
.el .IP "\f(CW$self\fR\->edit_file(filename=>..., cb=>sub{...})" 4
.IX Item "$self->edit_file(filename=>..., cb=>sub{...})"
Read a file, edit it with the provided callback, and save it if it has
changed. The \*(L"filename\*(R" parameter is the filename to read. The
\&\*(L"write_filename\*(R" parameter is the filename to write, defaulting to the same
name as the filename to read. The \*(L"cb\*(R" parameter is a reference to a
callback which takes the string of file contents and returns the string to
write back. Often the callback will simply perform a search and replace.
.SH "DISTRIBUTION"
.IX Header "DISTRIBUTION"
Verilog-Perl is part of the free Verilog \s-1EDA\s0
software tool suite. The latest version is available from \s-1CPAN\s0 and from
.
.PP
Copyright 2006\-2022 by Wilson Snyder. This package is free software; you
can redistribute it and/or modify it under the terms of either the \s-1GNU\s0
Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
.SH "AUTHORS"
.IX Header "AUTHORS"
Wilson Snyder
.SH "SEE ALSO"
.IX Header "SEE ALSO"
Verilog-Perl