NAME¶

GENLIB_LORES - add a logical resistor to the current netlist figure

SYNOPSYS¶

#include <genlib.h>
void GENLIB_LORES(type,resi,rcon1,rcon1,name)
char type ;
double resi ;
char ∗rcon1, ∗rcon1 ;
char ∗name ;

ORIGIN¶

This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France.

Web : http://asim.lip6.fr/recherche/alliance/
E-mail : alliance-users@asim.lip6.fr

PARAMETERS¶

type

Type of the resistor to be created in the current figure

resi

Resistance value.

rcon1, rcon1

Name of the signals on which the given resistor connectors are to be linked.

name

Resistor name. The unicity of the name is not checked.

DESCRIPTION¶

LORES adds a logical resistor to the current working figure. This resistor has each of its pin logicaly linked to the adequat signal given as parameter. For the time being, the type attribut may take the following value:

RESMIM

for a MIM (metal) type resistor.

ERROR¶

"GENLIB_LORES impossible : missing GENLIB_DEF_LOFIG"

EXAMPLE¶

#include <genlib.h>
int main(int argc,char ∗argv[])
{


  /∗ Create a figure to work on, a parallel resistor ∗/


  GENLIB_DEF_LOFIG("parallel_res") ;


  /∗ Define interface ∗/


  GENLIB_LOCON("i",IN,"input") ;


  GENLIB_LOCON("f",OUT,"output") ;


  /∗ Add resistors ∗/


  GENLIB_LORES(RESMIM,5.1,"input","output","res1") ;


  GENLIB_LORES(RESMIM,5.2,"input","output","res2") ;


  /∗ Save all that on disk ∗/


  GENLIB_SAVE_LOFIG() ;


  return 0 ;
}

SEE ALSO¶

genlib(1), GENLIB_BUS(3), GENLIB_ELM(3), GENLIB_LOINS(3), GENLIB_LOCON(3).

BUG REPORT¶

This tool is under development at the ASIM department of the LIP6 laboratory.
We need your feedback to improve documentation and tools.