Types¶

Each atomic operation operates on a specific type. The type to use is indicated in the function name. The available types that can be used are:

For example, the function to atomically add two integers is called atomic_add_int().

Certain architectures also provide operations for types smaller than “int”.

These must not be used in MI code because the instructions to implement them efficiently might not be available.

Acquire and Release Operations¶

By default, a thread's accesses to different memory locations might not be performed in program order, that is, the order in which the accesses appear in the source code. To optimize the program's execution, both the compiler and processor might reorder the thread's accesses. However, both ensure that their reordering of the accesses is not visible to the thread. Otherwise, the traditional memory model that is expected by single-threaded programs would be violated. Nonetheless, other threads in a multithreaded program, such as the FreeBSD kernel, might observe the reordering. Moreover, in some cases, such as the implementation of synchronization between threads, arbitrary reordering might result in the incorrect execution of the program. To constrain the reordering that both the compiler and processor might perform on a thread's accesses, the thread should use atomic operations with acquire and release semantics.

Most of the atomic operations on memory have three variants. The first variant performs the operation without imposing any ordering constraints on memory accesses to other locations. The second variant has acquire semantics, and the third variant has release semantics. In effect, operations with acquire and release semantics establish one-way barriers to reordering.

When an atomic operation has acquire semantics, the effects of the operation must have completed before any subsequent load or store (by program order) is performed. Conversely, acquire semantics do not require that prior loads or stores have completed before the atomic operation is performed. To denote acquire semantics, the suffix “_acq” is inserted into the function name immediately prior to the “_⟨type⟩” suffix. For example, to subtract two integers ensuring that subsequent loads and stores happen after the subtraction is performed, use atomic_subtract_acq_int().

When an atomic operation has release semantics, the effects of all prior loads or stores (by program order) must have completed before the operation is performed. Conversely, release semantics do not require that the effects of the atomic operation must have completed before any subsequent load or store is performed. To denote release semantics, the suffix “_rel” is inserted into the function name immediately prior to the “_⟨type⟩” suffix. For example, to add two long integers ensuring that all prior loads and stores happen before the addition, use atomic_add_rel_long().

The one-way barriers provided by acquire and release operations allow the implementations of common synchronization primitives to express their ordering requirements without also imposing unnecessary ordering. For example, for a critical section guarded by a mutex, an acquire operation when the mutex is locked and a release operation when the mutex is unlocked will prevent any loads or stores from moving outside of the critical section. However, they will not prevent the compiler or processor from moving loads or stores into the critical section, which does not violate the semantics of a mutex.

Multiple Processors¶

In multiprocessor systems, the atomicity of the atomic operations on memory depends on support for cache coherence in the underlying architecture. In general, cache coherence on the default memory type, VM_MEMATTR_DEFAULT, is guaranteed by all architectures that are supported by FreeBSD. For example, cache coherence is guaranteed on write-back memory by the amd64 and i386 architectures. However, on some architectures, cache coherence might not be enabled on all memory types. To determine if cache coherence is enabled for a non-default memory type, consult the architecture's documentation.

Semantics¶

This section describes the semantics of each operation using a C like notation.

atomic_add(p, v)

*p += v;

atomic_clear(p, v)

*p &= ~v;

atomic_cmpset(dst, old, new)

if (*dst == old) {
	*dst = new;
	return (1);
} else
	return (0);

The atomic_cmpset() functions are not implemented for the types “char”, “short”, “8”, and “16”.

atomic_fetchadd(p, v)

tmp = *p;
*p += v;
return (tmp);

The atomic_fetchadd() functions are only implemented for the types “int”, “long” and “32” and do not have any variants with memory barriers at this time.

atomic_load(p)

return (*p);

The atomic_load() functions are only provided with acquire memory barriers.

atomic_readandclear(p)

tmp = *p;
*p = 0;
return (tmp);

The atomic_readandclear() functions are not implemented for the types “char”, “short”, “ptr”, “8”, and “16” and do not have any variants with memory barriers at this time.

atomic_set(p, v)

*p |= v;

atomic_subtract(p, v)

*p -= v;

atomic_store(p, v)

*p = v;

The atomic_store() functions are only provided with release memory barriers.

atomic_swap(p, v)

tmp = *p;
*p = v;
return (tmp);

The atomic_swap() functions are not implemented for the types “char”, “short”, “ptr”, “8”, and “16” and do not have any variants with memory barriers at this time.

atomic_testandclear(p, v)

bit = 1 << (v % (sizeof(*p) * NBBY));
tmp = (*p & bit) != 0;
*p &= ~bit;
return (tmp);

atomic_testandset(p, v)

bit = 1 << (v % (sizeof(*p) * NBBY));
tmp = (*p & bit) != 0;
*p |= bit;
return (tmp);

The atomic_testandset() and atomic_testandclear() functions are only implemented for the types “int”, “long” and “32” and do not have any variants with memory barriers at this time.

The type “64” is currently not implemented for any of the atomic operations on the arm, i386, and powerpc architectures.