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riscemu(1) riscemu riscemu(1)

NAME

riscemu - RISC-V emulator in Python.

SYNOPSIS



 riscemu [-h] [--options OPTIONS] [--syscall-opts SYSCALL_OPTS] [--instruction-sets INSTRUCTION_SETS] 


            [--stack_size [STACK_SIZE]] [--flen [FLEN]] [-v] [--interactive] [--ignore-exit-code]


            file.asm [file.asm ...]

DESCRIPTION

This emulator contains:

-
RISC-V Assembly parser
-
RISC-V Assembly loader
-
Emulation for most parts of the basic RISC-V instruction set and the M and A extensions
-
Naive memory emulator
-
Basic implementation of some syscalls
-
A debugging environment

OPTIONS

- Do not treat all horizontal whitespace as equivalent
- Allows changing a default match keyword CHECK to an arbitrary keyword
- Adds implicit CHECK-NOT check that works on every input line
- Display available options
show this help message and exit --options OPTIONS, -o OPTIONS Toggle options. Available options are:
Disable ebreak instructions
Don't add symbols for SCALL_EXIT and others
If set, exceptions won't trigger the debugger
Accept "add rd, rs, imm" instruction (instead of addi)
Allow an unlimited number of registers
Load a libc-like runtime (for malloc, etc.)
Don't exit with the programs exit code. --syscall-opts SYSCALL_OPTS, -so SYSCALL_OPTS --instruction-sets INSTRUCTION_SETS, -is INSTRUCTION_SETS Instruction sets to load, available are: RV32I, RV32M, RV32A, RV32F, RV32D, Zicsr, RV_Debug. All are enabled by default --stack_size [STACK_SIZE] Stack size of loaded programs, defaults to 8MB
hardware FLEN, either 32 or 64. Defaults to 64
Verbosity level (can be used multiple times)
Launch the interactive debugger instantly instead of loading any programs
Ignore exit code of the program and always return 0 if the program ran to completion.

REPORTING BUGS

To report a bug please visit riscemu issues tracking system at: https://github.com/AntonLydike/riscemu/issues

AUTHORS

This manual page was written by Bo YU <tsu.yubo@gmail.com> for the Debian project (but may be used by others).

31 July 2024